• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed to a height or thickness equal to or preferably exceeding the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer formed above the first dielectric layer; one or more local interconnects formed in the second dielectric layer; and a thin third dielectric layer formed over the second dielectric layer and the local interconnects therein. The thin third dielectric layer has a thickness not exceeding about 2000 Å, and preferably ranging from about 1000 Å to about 1500 Å. A first layer of metal interconnects is formed over the thin third dielectric layer. Conventionally formed filled contact openings extend from the substrate through the first dielectric layer to either filled vias or a local interconnect in the second dielectric layer. The metal interconnects are electrically connected to either filled vias or one or more local interconnects in the second dielectric layer by filled shallow vias in the thin third dielectric layer. The shallow vias in the thin third dielectric layer are preferably filled with the same metals used to form the first layer of metal interconnects.
    公开号:US20010005057A1
    申请号:US09/790,821
    申请日:2001-02-22
    公开日:2001-06-28
    发明作者:Nicholas Pasch；Rajat Rakkhit
    申请人:Pasch Nicholas F.；Rajat Rakkhit；
    IPC主号:H01L21-76895
    专利说明:
    [0001] 1. Field of the Invention [0001]
    [0002] This invention relates to integrated circuit structures having local interconnects. More particularly, this invention relates to an integrated circuit structure wherein a local interconnect level is separated from both the underlying substrate and the overlying first metal interconnect level in a manner which permits both the local interconnect level and the first metal interconnect level to bridge over underlying electrically conductive regions without any undue increase in either the capacitance of the structure or the resistance paths through contact openings/vias extending from the substrate to the first metal interconnect layer. [0002]
    [0003] 2. Description of the Related Art [0003]
    [0004] Conventionally an integrated circuit structure may be constructed with local interconnects as shown in typical prior art FIG. 1. Typically, such local interconnects are formed in between raised portions of the integrated circuit devices, such as in between gate electrodes. Such local interconnects may be formed using the same conductive material as the filler material, e.g., tungsten, used to fill the contact openings which provide electrical connection to other portions of the integrated circuit device such as the source/drain regions. The local interconnects may also be formed using the same material used in forming the gate electrode, e.g., doped polysilicon. In either case, the material used for the local interconnect characteristically does not possess the same low resistance as the metal used for conventional metal interconnect layers, e.g., aluminum, but is more easily planarized by polishing techniques (particularly when tungsten is used as the local interconnect material). Since such local interconnects are conventionally formed at or about the same level as the gate electrode, they permit some low level electrical connections to be made between adjacent conductive areas at a level lower than the first metal interconnect level. However, since they are typically constructed at the same level as the gate electrodes and have no insulation below separating them from the underlying substrate, their use is limited to the interconnecting of adjacent conductive regions (they cannot bridge over conductive regions) and hence they are referred to as “local interconnects”. [0004]
    [0005] FIG. 1 shows a typical prior art integrated circuit structure with a local interconnect formed thereon. In the structure illustrated in FIG. 1, a semiconductor substrate [0005] 2 may be provided, by way of example, with several MOS transistors constructed thereon which are electrically isolated from one another by field oxide 6 a, and from other devices in substrate 2 by field oxide 6 b and 6 c. The MOS devices respectively comprise source/drain regions 10 and 12 with a gate electrode 14 therebetween; and source/drain regions 20 and 22 with a gate electrode 24 therebetween. A first dielectric layer 30, formed of a dielectric material such as silicon oxide (SiO2) and having a thickness of from about 3500 Å to about 5000 Å (after planarization), is deposited over this structure and then planarized back to about the level of gate electrodes 14 and 24, e.g., by an etch step or a chemical mechanical polishing process.
    [0006] Filled contact openings [0006] 32 and 34 are then respectively formed through dielectric layer 30 down to underlying source/drain regions 10 and 22 and then filled with a metal such as tungsten. At the same time, a portion of dielectric layer 30 is etched down to the level of source/drain regions 12 and 20 and field oxide 6 b, and then filled with tungsten, to form filled opening 36 which comprises a local interconnect to electrically connect source/drain region 12 with source/drain region 20. Thus, when contact openings 32 and 34 are filled with a conductive material 44, such as tungsten metal, opening 36 is also filled at the same time with the same conductive material, thereby forming local interconnect 36 to electrically interconnect adjacent source/drain regions 12 and 20 together.
    [0007] After formation of the first level of filled contact openings/vias and the local interconnects, a second dielectric layer [0007] 50 (which may also comprise SiO2 and which may also have a thickness of from about 3500 Å to about 5000 Å) is formed over the structure. A filled via 52 is then formed through dielectric layer 50 to and in registry with underlying filled contact opening 32 to provide electrical contact to source/drain region 10; a filled via 54 is formed through layer 50 to and in registry with gate electrode 14; a filled via 56 is formed through layer 50 to and in registry with gate electrode 24, and a filled via 58 is formed through layer 50 to and in registry with filled contact opening 34 to provide electrical contact to source/drain region 22. Filled vias 52, 54, 56, and 58 are also typically filled with tungsten. A first layer 60 of metal interconnects, illustrated as 60 a-60 c and typically comprising a metal more highly conductive than tungsten such as aluminum or copper, is then formed over dielectric layer 50 to provide respective electrical contact to filled vias 52, 54, 56, and 58 and to provide interconnections between these regions and other regions (not shown) on the integrated circuit structure.
    [0008] In this prior art construction it will be readily apparent that first metal interconnect layer [0008] 60 can bridge over other underlying conductive regions, e.g., over local interconnect 36, because of the presence of underlying dielectric layer 50. However, it will be equally apparent from examination of FIG. 1, that while underlying local interconnect 36 does permit electrical interconnection between adjacent electrodes or conductive regions below the level of first metal interconnect layer 60, this electrical connection is called a “local interconnect” because only adjacent (or “local”) conductive regions (diffusion regions) may be electrically connected together in this manner. This is because local interconnect 36 is formed directly over the surface of substrate 2, i,e, it does not have an underlying dielectric layer unlike first metal interconnect layer 60. This, of course, limits the usefulness of local interconnects.
    [0009] However, despite the drawbacks of local interconnects, they do have useful functions, even though somewhat limited compared to conventional metal interconnect layers. For example, even when the tungsten material comprising the local interconnect is not deposited over substrate [0009] 2 in the same step used to fill contact openings, the contact openings and local interconnect openings may be cut through the dielectric layer at the same time. There are other advantages to forming such a local interconnect at the same level as the contact opening and using the same material as used to fill the contact opening.
    [0010] For example, it will be noted that the sum of the heights of filled contact opening [0010] 32 and filled via 52 from source/drain region 10 to first metal interconnect layer 60 (the combined thickness of dielectric layers 30 and 50) is approximately the same as it would have been had local interconnect 36 not been formed in the structure. That is, the construction of local interconnect 36 in dielectric layer 30 did not lengthen the resistive path through the tungsten filler material from source/drain region 10 to metal interconnect layer 60. Thus, where the use of local interconnects can sometimes eliminate the need for one layer of metal interconnects, the total resistive path through the filled tungsten contact openings/vias in the overall integrated circuit structure may, as a result, be shortened, thus lowering the total resistance in the structure and increasing its speed.
    [0011] However, it would be even more advantageous if one could utilize local interconnects without limiting their use to only strapping or interconnecting adjacent conductive regions, i.e., if the local interconnect could bridge over conductive regions or other interconnects. An alternative construction, illustrated in FIG. 2, alters the construction of the local interconnect to permit it to bridge or cross over underlying conductive regions. [0011]
    [0012] In FIG. 2, where like structures are shown with like numerals, dielectric layer [0012] 30′ (which may also comprise SiO2) is formed over the underlying MOS structures and then planarized back to a thickness which may be the same as the height of gate electrodes 14 and 24, e.g., from about 3500 Å to about 5000 Å, but preferably to a thickness slightly (about 500 Å to about 1000 Å) in excess of the height of gate electrodes 14 and 24 for a reason which will be explained below.
    [0013] Similarly to the structure of FIG. 1, filled contact opening [0013] 32′ is formed through dielectric layer 30′ to underlying source/drain region 10 in substrate 2 and filled contact opening 34′ is formed through dielectric layer 30′ to source/drain region 22 in substrate 2. However, unlike the structure shown in FIG. 1, a filled contact opening 132 is formed through dielectric layer 30′ to source/drain region 12 in substrate 2; and filled contact openings 134 and 136 are respectively formed through dielectric layer 30′ to gate electrode 14 and gate electrode 24. In each case, the filled contact openings may be filled with tungsten, as in the previous embodiment described for FIG. 1.
    [0014] After formation of filled contact openings [0014] 32′, 34′, 132, 134, and 136 in dielectric layer 30′, a further dielectric layer 50′ (which may also comprise SiO2 and which may have the same thickness range as layer 50) is formed over dielectric layer 30′ and the filled contact openings therein. A filled via 52′ is formed in dielectric layer 50′ extending down to (and in registry with) underlying filled contact opening 32′, a filled via 54′ is formed in dielectric layer 50′ down to (and in registry with) underlying filled contact opening 134 over gate electrode 14, and a filled via 58′ is formed in dielectric layer 50′ down to (and in registry with) underlying filled contact opening 34′.
    [0015] However, in this embodiment, a local interconnect [0015] 156 is formed in second dielectric layer 50′ over (and in registry with) underlying filled contact opening 132 and filled contact opening 136, thereby connecting together source/drain region 12 and gate electrode 24. Furthermore, unlike the previous embodiment of FIG. 1, local interconnect 136 in FIG. 2 is shown bridging source/drain region 20 (electrical contact can be made to source/drain region 20 at another non-illustrated point in the structure along an axis perpendicular to the plane of the figure). Thus, this embodiment now permits the flexibility of use of the local interconnect which is lacking in the structure of FIG. 1. Furthermore, when the thickness of first dielectric layer 30′ exceeds the height of gate electrodes 14 and 24, local interconnect 136 can even bridge such raised gate electrodes.
    [0016] Nevertheless, there is a drawback with the use of the FIG. 2 structure which, at least in part, negates the advantages of the FIG. 2 structure over the FIG. 1 structure. This disadvantage is illustrated in FIG. 2 by the formation of the first metal interconnect layer [0016] 60′ directly over second dielectric layer 50′ as shown. Thus, illustrated individual metal interconnects 60 a′-60 d′ are formed directly above second dielectric layer 50′. This puts the undersurface of first metal interconnect 60 b′, for example, directly in contact with the upper surface of local interconnect 156. Those skilled in the art will readily appreciate that the drawback in FIG. 1 of placing local interconnect 36 directly above substrate 2 (so that conductive regions in substrate 2 cannot be bridged by the local interconnects) has now simply been transferred to the interface between the local interconnect layer and the first metal interconnect layer. That is, now the first layer of metal interconnects cannot bridge over the local interconnects. This is actually a more serious problem than the problem encountered in the structure of FIG. 1, since the first metal interconnect layer is conventionally a more crowded layer with many more interconnects than at the local interconnect level, and the inability of the first metal interconnect level to cross over underlying local interconnects is a disability which cannot and will not be tolerated by design (layout) engineers.
    [0017] While it might seem to be obvious to simply add another dielectric layer to the FIG. 2 structure, between the local interconnect layer and the first metal interconnect layer, to solve the bridging problem, this, too, cannot be tolerated because the presence of another dielectric layer between the first metal interconnect and the substrate results in the need to provide another layer of tungsten-filled vias through this third dielectric layer, thus adding to the cost and complexity of the structure as well as increasing the defect density. [0017]
    [0018] Thus, it remains a desire and goal to provide an integrated circuit structure with local interconnects and a first metal interconnect layer wherein both the local interconnect layer and the first metal interconnect layer may be capable of bridging over underlying conductive region in the integrated circuit structure without, however, substantial addition to either the resistance or the capacitance of the structure. [0018] SUMMARY OF THE INVENTION
    [0019] Quite surprisingly, we have discovered that an integrated circuit structure may be provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed over the structure to a height or thickness equal to or preferably exceeding the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer formed above the first dielectric layer; one or more local interconnects formed in the second dielectric layer; a thin third dielectric layer formed over the second dielectric layer and the local interconnects therein, wherein the third dielectric layer has a thickness not exceeding about 2000 Å, and preferably ranging from about 1000 Å to about 1500 Å; and a first layer of metal interconnects formed over the thin third dielectric layer. Conventionally formed filled contact openings extend from the substrate through the first dielectric layer to either filled vias or a local interconnect in the second dielectric layer. The metal interconnects are electrically connected to either filled vias or one or more local interconnects in the second dielectric layer by filled shallow vias in the thin third dielectric layer. The shallow vias in the thin third dielectric layer are preferably filled with the same metals used to form the first layer of metal interconnects. [0019] BRIEF DESCRIPTION OF THE DRAWINGS
    [0020] FIG. 1 is a fragmentary vertical cross-sectional view of a prior art integrated circuit structure showing conventional local interconnects formed over a semiconductor substrate and in contact with portions of the substrate, and a layer of metal interconnects formed over the local interconnects and separated therefrom by a dielectric layer through which filled vias or contact openings are formed. [0020]
    [0021] FIG. 2 is a fragmentary vertical cross-sectional view of another integrated circuit structure showing local interconnects formed over a first dielectric layer formed over the semiconductor substrate, with a layer of metal interconnects then formed directly over the local interconnect layer. [0021]
    [0022] FIG. 3 is a fragmentary vertical cross-sectional view of the integrated circuit structure of the invention showing local interconnects formed over a first dielectric layer formed over the semiconductor substrate, with a thin dielectric layer formed over the local interconnects to separate them from a layer of metal interconnects formed over the thin dielectric layer. [0022]
    [0023] FIG. 4 is a fragmentary top view of the structure of FIG. 3. [0023] DETAILED DESCRIPTION OF THE INVENTION
    [0024] The invention comprises an integrated circuit structure provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed over the underlying integrated circuit structure to a height or thickness preferably exceeding the height of the highest conductive regions of the underlying integrated circuit devices, which usually will be the gate electrode; a second dielectric layer formed above the first dielectric layer; one or more local interconnects formed in the second dielectric layer; a thin third dielectric layer formed over the second dielectric layer and the local interconnects therein, wherein the third dielectric layer has a thickness not exceeding about 2000 Å, and preferably ranging from about 1000 Å to about 1500 Å; and a first layer of metal interconnects formed over the thin third dielectric layer. Conventionally formed filled contact openings extend from the substrate through the first dielectric layer to either filled vias or a local interconnect in the second dielectric layer. The metal interconnects are electrically connected to either filled vias or one or more local interconnects in the second dielectric layer by filled shallow vias in the third dielectric layer. The shallow vias in the thin third dielectric layer are preferably filled with the same materials and desirably at the same time as that used to form the first layer of metal interconnects. [0024]
    [0025] Since the local interconnect in the preferred embodiment of the invention is not located at the same level as the gate electrode, for purposes of this invention the term “local interconnect” is intended to mean the first patterned layer of interconnects formed above the substrate and formed from a conductive material having a higher resistance than the higher levels of patterned metal interconnect layers. [0025]
    [0026] By use of the term “thin dielectric” herein is meant a dielectric material not exceeding about 2000 Å in thickness and preferably having a thickness ranging from about 1000 Å to about 1500 Å, although even thinner dielectric layers may be used in some instances. This is in contrast to the conventional dielectric layer between local interconnects and metal interconnects (or between layers of metal interconnects) having a thickness usually ranging from about 7000 Å to about 10,000 Å. [0026]
    [0027] What is surprising about the invention is the discovery that a thin dielectric layer could be used to separate the local interconnect layer from the first metal interconnect layer without unduly increasing the overall capacitance of the structure, and without unduly increasing the resistance path from portions of the underlying integrated circuit devices to the metal interconnects. [0027]
    [0028] First of all, with respect to the resistance, the use of a thin dielectric layer between the local interconnect layer and the first metal interconnect layer means that the height or thickness of a via through this thin dielectric layer does not unduly increase the resistance because of the short additional path of the via through the thin dielectric layer. However, what was further surprising about this was that by shortening the height of the via (without changing the diameter), the aspect ratio of the via was lowered, thus making it possible to eliminate the use of the high resistance tungsten metal filler (which is normally used to fill vias with high aspect ratios because of the superior via-filling ability of tungsten). Instead, the shallow vias can be filled at the same time (and with the same low resistance material) as the blanket deposition of the metal layer over the thin dielectric layer, e.g., the aluminum or copper layer which will be patterned to form the metal interconnects. Since the shallow (low aspect ratio) via can be filled with the same low resistance metal used to form the metal interconnects, and since the via height is very short (1000 Å to 2000 Å compared to 7000 Å to 10,000 Å), the resistance added to the circuit by the presence of the thin dielectric of the invention is negligible. [0028]
    [0029] Secondly, and perhaps even more surprising because of its subtlety, is the negligible effect of the thin dielectric of the invention on the overall capacitance of the integrated circuit structure. In previous integrated circuit structures, where the aspect ratio (height/width) of contact openings and vias was at 2:1 or less, the width of the interconnects or lines was sufficiently large so that the vertical capacitance, i.e., the capacitance through the thickness of the dielectric layer from one level of interconnect to the next level, contributed most of the capacitance of the circuit, thus resulting in the need and use of thick dielectric layers. However, as the aspect ratios increased and the line widths decreased the vertical component of the capacitance decreased. At the same time, the horizontal spacing between vias and between lines (as well as between vias and lines) shrank sufficiently so that the horizontal capacitance between adjacent conductive surfaces, such as between adjacent lines, has increased, thereby becoming a major contributor to the overall capacitance of the circuitry. The thickness of the dielectric layers, however, has not changed, despite such changes in aspect ratios and linewidths, because at higher metal interconnect layer levels, the length of the lines, and the number of crossings of lines, is such that vertical capacitance still is a major contributor to capacitance. [0029]
    [0030] Thus, it was surprisingly realized that at least the first dielectric layer separating the local interconnect layer and the first metal interconnect layer could be made considerably thinner without unduly increasing the overall capacitance of the circuitry, because of the greater contribution of the horizontal capacitance to the overall capacitance of the circuitry (at least at such local interconnect/first metal interconnect levels). [0030]
    [0031] It should be noted that while the invention is principally directed to the local interconnect and first metal interconnect levels, and the separation of these two levels by a special thin dielectric layer, there may be some instances where the provision of such a thin dielectric layer between the first and second metal interconnect layers may also be appropriate, depending upon the density of the interconnects and the number of crossovers between such levels which could, if too high, add an unacceptable amount of capacitance to the integrated circuit structure if such a thin dielectric layer was used. Thus, under appropriate circumstances where the additional vertical capacitance will be insignificant, it is within the scope of the invention to also utilize the thin dielectric layer of the invention between the first and second levels of metal interconnects. [0031]
    [0032] In any event, the utility of the invention is particularly directed toward the lowest levels of interconnects, such as the local interconnect and first metal interconnect levels (and possibly between the first and second metal interconnect levels), where the length of the lines is short, to thereby minimize added vertical capacitance. By “short”, with respect to line and interconnect length, is meant not more than about 50 microns in length, preferably not more than about 20 microns, more preferably about 10 microns, and most preferably not more than about 5 microns in length. [0032]
    [0033] Turning now to FIGS. 3 and 4, the structure and process of the invention is illustrated. As in the prior art structure illustrated in FIG. 1, a semiconductor substrate [0033] 2 may be provided, by way of example, with several MOS transistors constructed thereon which are electrically isolated from one another by field oxide 6 a, and from other devices in substrate 2 by field oxide 6 b and 6 c. The illustrated MOS devices respectively comprise source/drain regions 10 and 12 with a gate electrode 14 therebetween; and source/drain regions 20 and 22 with a gate electrode 24 therebetween.
    [0034] In accordance with the invention, a first dielectric layer [0034] 130, formed of a dielectric material such as silicon oxide (SiO2), is deposited over this structure and then planarized back, by an etch step or a chemical mechanical polishing process, to a level which is preferable slightly higher that gate electrodes 14 and 24 (which range in height from about 3500 Å to about 5000 Å). By slightly higher is meant from about 500 Å to about 1000 Å higher than the top of gate electrodes 14 and 24. Contact openings 132, 134, 136, 138, 140, and 142 are then cut through dielectric layer and filled with a conductive metal such as tungsten capable of filling a contact opening having a diameter of, for example, approximately 0.25 micrometers (μm).
    [0035] The surface of the structure may be again planarized at this time, for example, by chemical mechanical polishing (CMP), to remove any of the contact opening filler material from the surface of dielectric layer [0035] 130. A second dielectric layer 150 is then formed over dielectric layer 130 to a thickness which, when added to the thickness of dielectric layer 130, will equal a total thickness of both dielectric layers of from about 7000 Å to about 10,000 Å.
    [0036] Openings are then cut through dielectric layer [0036] 150 for the formation of vias to the previously described underlying filled contact openings, as well as for formation of local interconnects. The filled vias, such as illustrated filled vias 152, 154, 156, and 158, and the local interconnects, such as illustrated local interconnect 160, are then formed by filling the openings with a conductive material (such as tungsten) capable of filling vias having a diameter of, for example, approximately 0.25 μm. The structure may then be subject to a further planarization, such as a dry etch step or a chemical mechanical polishing step to remove the filler material form the surface of dielectric material 150.
    [0037] In accordance with the invention, a third dielectric layer [0037] 170, comprising a thin dielectric layer, is formed over dielectric layer 150 after the formation of the filled vias, e.g., filled vias 152-158, and the local interconnects, e.g., local interconnect 160. Thin third dielectric layer 170 is formed over dielectric layer 150 to a thickness not exceeding about 2000 Å, and preferably ranging from about 1000 Å to about 1500 Å, although in some instances, dielectric layer 170 may be as thin as 500 Å. This dielectric layer may again comprise silicon oxide (SiO2). Alternatively, thin dielectric layer 170 may comprise a material having an even lower dielectric constant than silicon oxide (i.e., lower than 3.8) to further reduce any capacitance added to the integrated circuit structure by the presence of third dielectric layer 170. Examples of such dielectric materials having dielectric constants less than 3.5 include fluorinated perylene, fluorinated SiO2, and hydrogen silsesquioxane. Lower dielectric constant materials for use in the formation of thin dielectric layer 170 can also be formed from modified silicon oxide, as described and claimed in U.S. Pat. Nos. 5,393,712, 5,470,801, and 5,598,026, all assigned to the assignee of this invention.
    [0038] After formation of thin dielectric layer [0038] 170, vias are cut through layer 170 to the previously described underlying filled vias and local interconnects as desired. Thus, as illustrated in FIG. 3, vias 172, 173, 174 and 176, 177, 178 are cut through dielectric layer 170 to respectively connect with underlying filled vias 152 and 154, local interconnect 160, and filled vias 156 and 158.
    [0039] It should be pointed out that the diameters of vias [0039] 172, 173, 174 and 176, 177, 178 are preferably the same as that of previously formed vias 152 et al., i.e., about 0.25 μm. In view of the relative difference in thickness between dielectric layer 170 and underlying dielectric layer 150, forming vias through layer 170 with the same diameter as the vias through layer 150 results in the formation of vias in layer 170 of much smaller aspect ratios (height/width) than the vias previously formed in layer 150. As a result of this, it has been found that, at least in some instances, the need for a separate step to fill the shallow vias formed in thin dielectric layer 170 with special filler material, e.g., tungsten, can be eliminated. That is, the shallow low aspect ratio vias cut through dielectric layer 170 may be filled during the subsequent blanket deposit of a patternable metal, such as aluminum, over dielectric layer 170 for the formation of the first metal interconnect layer.
    [0040] It should also be noted that an added bonus of the practice of the invention is that the photoresist etch mask used to form the shallow vias through thin insulation layer [0040] 170 need not be a thick photoresist layer, since the via-etching step is very short (due to the thinness of dielectric layer 170) and therefore less of the photoresist mask will be eroded. The use of a thinner photoresist mask, in turn, will increase the resolution and accuracy of pattern size and generally improve the masking process.
    [0041] The filling of vias [0041] 172, 173, 174 and 176, 177, 178 with the same metal used to form the first layer of metal interconnects is advantageous from the standpoint of the lower resistance of metal interconnect material, such as aluminum (or copper), compared to conventional via filler materials, such as tungsten (which are selected for their via-filling capabilities, not their low resistance). This feature, coupled with the shortened length (height) of the vias (due to the thinness of dielectric layer 170), results in a minimizing of the resistance added to the integrated circuit structure by the addition of thin dielectric layer 170.
    [0042] Still referring to FIG. 3, a blanket layer of a patternable metal, such as aluminum, is deposited over dielectric layer [0042] 170 and into (and filling) vias 172, 173, 174 and 176, 177, 178, in preparation for the formation of metal interconnects 180 a-180 f. After deposition of the blanket layer of metal, such as aluminum, and the filling of the vias in dielectric layer 170, the metal layer is patterned, as shown in FIGS. 3 and 4, using a suitable photoresist mask and an anisotropic etch system, such as a chlorine plasma etch for aluminum. It should be observed here that while the anisotropic etch will normally be designed to stop at dielectric layer 170, overetching into layer 170, or even entirely through layer 170 to underlying dielectric layer 150, is harmless, since a further dielectric layer will be deposited over and in between metal interconnects 180 a-180 f (and over any exposed surfaces of dielectric layers 150 and 170 in between the metal interconnects) after the formation of the metal interconnects.
    [0043] It will be noted in FIG. 3 that the filled vias formed in layer [0043] 150 and the local interconnects are in registry and in contact with the respective underlying filled contact openings to thereby complete the respective electrical paths, for example, from source/drain region 10 to metal interconnect 180 a through filled contact opening 132, filled via 152, and filled via 172.
    [0044] Alternatively, if copper is used to form metal interconnects [0044] 180 a-180 f, a thin layer of copper may be first deposited over dielectric layer 170 to fill vias 172, 173, 174 and 176, 177, 178 with copper, followed by a chemical mechanical polishing step to remove any copper from the surface of layer 170. A fourth dielectric layer may then be deposited over layer 170 and etched to form trenches through the entire thickness of the fourth dielectric layer, the trenches corresponding to the desired pattern of metal interconnects, thereby exposing the copper-filled vias. A layer of copper is then deposited over the fourth dielectric layer and in the trenches, thereby making contact with the copper-filled vias. The structure is then subject to a further chemical mechanical polishing to remove all copper on the surface of the fourth dielectric layer, leaving the desired pattern of copper interconnects in the trenches.
    [0045] Regardless of whether copper or aluminum (or any other metal of equivalent low resistance) is used to form the metal interconnects, the result is an integrated circuit structure having a local interconnect level capable of bridging conductive regions in the substrate, and a first metal interconnect level separated from the local interconnect level by a thin dielectric layer. The thin dielectric layer, having a thickness not exceeding about 2000 Å, and preferably having a thickness range of from about 1000 Å to about 1500 Å, does not add significant resistance or capacitance to the circuit. [0045]
    [0046] The added resistance is minimal because of the reduced path length of the additional via through the thin dielectric layer and the reduced aspect ratio of the vias through the thin dielectric layer which makes possible the filling of the vias in the thin dielectric layer with the same low resistance metal used to form the metal interconnect level. [0046]
    [0047] The added capacitance is minimal because of the low density of crossover lines between the local interconnect/first metal interconnect levels and the close horizontal spacing between adjacent vias and/or adjacent lines which provides the majority of the capacitance as horizontal components, and reduces the significance of vertical capacitance components. [0047]
    权利要求:
    Claims (21)
    [1" id="US-20010005057-A1-CLM-00001] 1. In an integrated circuit structure formed on a semiconductor substrate with a local interconnect layer, and a first metal interconnect layer separated from said local interconnect layer by a dielectric layer, the improvement comprising a dielectric layer separating said local interconnect layer from said first metal layer comprising a thin dielectric layer having a thickness not exceeding about 2000 Å.
    [2" id="US-20010005057-A1-CLM-00002] 2. The integrated circuit structure of
    claim 1 wherein a second dielectric layer is formed between said local interconnect layer and said substrate whereby first conductive regions on said substrate may be bridged by local interconnects used to electrically connect second conductive regions in said substrate.
    [3" id="US-20010005057-A1-CLM-00003] 3. The integrated circuit structure of
    claim 2 wherein said thin dielectric layer has a thickness ranging from about 1000 Å to about 2000 Å.
    [4" id="US-20010005057-A1-CLM-00004] 4. The integrated circuit structure of
    claim 2 wherein said thin dielectric layer has a thickness ranging from about 1000 Å to about 1500 Å.
    [5" id="US-20010005057-A1-CLM-00005] 5. The integrated circuit structure of
    claim 2 wherein a third dielectric layer is formed over said second dielectric layer and under said thin dielectric layer, said third dielectric layer having openings formed therein filled with a conductive material comprising said local interconnects.
    [6" id="US-20010005057-A1-CLM-00006] 6. The integrated circuit structure of
    claim 5 wherein said second dielectric layer has a plurality of filled contact openings therein connected at a lower end to one or more of said first and second conductive regions in said substrate.
    [7" id="US-20010005057-A1-CLM-00007] 7. The integrated circuit structure of
    claim 6 wherein one or more of said filled contact openings in said second dielectric layer are connected, at an upper end thereof, to one or more of said local interconnects in said third die layer.
    [8" id="US-20010005057-A1-CLM-00008] 8. The integrated circuit structure of
    claim 7 wherein said thin dielectric layer contains one or more shallow filled vias interconnecting said local interconnects in said third dielectric layer with one or more of said metal interconnects.
    [9" id="US-20010005057-A1-CLM-00009] 9. The integrated circuit structure of
    claim 8 wherein said shallow filled vias in said thin die layer are filled with the same metal used to form said metal interconnects.
    [10" id="US-20010005057-A1-CLM-00010] 10. An integrated circuit structure comprising:
    a) a semiconductor substrate;
    b) two or more integrated circuit devices constructed on and in said substrate;
    c) a first dielectric layer formed over said integrated circuit devices, with one or more filled contact openings extending through said first dielectric layer to said devices;
    d) a second dielectric layer formed over said first dielectric layer;
    e) filled vias and one or more local interconnects formed in said second dielectric layer extending down to said filled contact openings;
    f) a thin dielectric layer formed over said second dielectric layer and said filled vias and one or more local interconnects therein;
    g) shallow filled vias formed in said thin dielectric layer; and
    h) a patterned metal interconnect layer formed over said thin dielectric layer and in contact with said filled shallow vias.
    [11" id="US-20010005057-A1-CLM-00011] 11. The integrated circuit structure of
    claim 10 wherein said metal used to form said patterned metal interconnect layer also fills said shallow vias in said thin dielectric layer.
    [12" id="US-20010005057-A1-CLM-00012] 12. The integrated circuit structure of
    claim 10 wherein said thin dielectric layer has a thickness ranging from about 1000 Å to about 2000 Å.
    [13" id="US-20010005057-A1-CLM-00013] 13. The integrated circuit structure of
    claim 10 wherein said thin dielectric layer has a thickness ranging from about 1000 Å to about 1500 Å.
    [14" id="US-20010005057-A1-CLM-00014] 14. The integrated circuit structure of
    claim 10 wherein a second thin dielectric layer is formed over said first layer of metal interconnects, and a second metal interconnect layer is formed over said second thin dielectric layer.
    [15" id="US-20010005057-A1-CLM-00015] 15. In a process for forming an integrated circuit structure with a local interconnect layer and a first metal interconnect layer, the improvement which comprises forming a thin dielectric layer over said local interconnect layer to separate said local interconnect layer from said first metal interconnect layer.
    [16" id="US-20010005057-A1-CLM-00016] 16. The process for forming an integrated circuit structure of
    claim 15 including the steps of forming a second dielectric layer between said local interconnect layer and said substrate and bridging first conductive regions on said substrate by local interconnects to electrically connect second conductive regions in said substrate.
    [17" id="US-20010005057-A1-CLM-00017] 17. The process for forming an integrated circuit structure of
    claim 15 wherein said step of forming a thin dielectric layer further comprises forming a dielectric layer having a thickness ranging from about 1000 Å to about 2000 Å.
    [18" id="US-20010005057-A1-CLM-00018] 18. The process for forming an integrated circuit structure of
    claim 15 wherein said step of forming a thin dielectric layer further comprises forming a dielectric layer having a thickness ranging from about 1000 Å to about 1500 Å.
    [19" id="US-20010005057-A1-CLM-00019] 19. The process for forming an integrated circuit structure of
    claim 15 including the further steps of forming shallow vias in said thin die layer, and filling said shallow vias with the same metal used to form said first metal interconnect layer.
    [20" id="US-20010005057-A1-CLM-00020] 20. A process for forming an integrated circuit structure comprising:
    a) providing a semiconductor substrate having two or more integrated circuit devices constructed on and in said substrate;
    b) forming a first dielectric layer over said substrate and said integrated circuit devices;
    c) forming filled contact openings in said first dielectric layer extending through said first dielectric layer to said integrated circuit devices;
    d) forming a second dielectric layer over said first dielectric layer;
    e) forming filled vias and one or more local interconnects in said second dielectric layer extending down to said filled contact openings;
    f) forming a thin dielectric layer over said second dielectric layer and said filled vias and one or more local interconnects in said second dielectric layer;
    g) forming shallow filled vias in said thin dielectric layer; and
    h) forming a patterned metal interconnect layer over said thin dielectric layer and in contact with said filled shallow vias in said thin dielectric layer.
    [21" id="US-20010005057-A1-CLM-00021] 21. The process for forming an integrated circuit structure of
    claim 20 further comprising the step of filling said shallow vias in said thin dielectric layer with the same metal used to form said patterned metal interconnect layer.
    类似技术:
    公开号 | 公开日 | 专利标题
    US6486056B2|2002-11-26|Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level
    US10515933B2|2019-12-24|System, structure, and method of manufacturing a semiconductor substrate stack
    US6140238A|2000-10-31|Self-aligned copper interconnect structure and method of manufacturing same
    US4617193A|1986-10-14|Planar interconnect for integrated circuits
    US6468894B1|2002-10-22|Metal interconnection structure with dummy vias
    US6472317B1|2002-10-29|Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers
    EP1326276A2|2003-07-09|Interconnection structure in semiconductor device
    US8390038B2|2013-03-05|MIM capacitor and method of making same
    KR19990030228A|1999-04-26|Double damask processing method to provide dielectric layer between metal layer and organic metal
    WO1997022144A1|1997-06-19|Reverse damascene via structures
    US6235628B1|2001-05-22|Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer
    EP0534631B1|1999-01-07|Method of forming vias structure obtained
    US6348734B1|2002-02-19|Self-aligned copper interconnect architecture with enhanced copper diffusion barrier
    EP1182708A2|2002-02-27|High capacitance damascene capacitor
    EP0495974A1|1992-07-29|Trench conductors and crossover architecture
    US6017814A|2000-01-25|Structure and fabrication method for stackable, air-gap-containing low epsilon dielectric layers
    US5924006A|1999-07-13|Trench surrounded metal pattern
    US6380625B2|2002-04-30|Semiconductor interconnect barrier and manufacturing method thereof
    US5915201A|1999-06-22|Trench surrounded metal pattern
    JP2001053144A|2001-02-23|Semiconductor device and manufacturing method of the same
    US6218291B1|2001-04-17|Method for forming contact plugs and simultaneously planarizing a substrate surface in integrated circuits
    US6362092B1|2002-03-26|Planarization method on a damascene structure
    US20020106885A1|2002-08-08|Method of fabricating a slot dual damascene structure without middle stop layer
    US6472697B2|2002-10-29|Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
    US7112537B2|2006-09-26|Method of fabricating interconnection structure of semiconductor device
    同族专利:
    公开号 | 公开日
    US6239491B1|2001-05-29|
    US6486056B2|2002-11-26|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20060246726A1|2001-08-31|2006-11-02|Klaus Goller|Making contact with the emitter contact of a semiconductor|
    US20070272980A1|2006-05-05|2007-11-29|Angelo Magri|Semiconductor device with vertical current flow and low substrate resistance and manufacturing process thereof|
    US20080251924A1|2003-10-15|2008-10-16|Megica Corporation|Post Passivation Interconnection Schemes On Top Of The IC Chips|
    US20110215479A1|2008-11-14|2011-09-08|Thomas Schulz|Feature Patterning Methods and Structures Thereof|
    US20110248283A1|2010-04-07|2011-10-13|Jianjun Cao|Via structure of a semiconductor device and method for fabricating the same|
    US9881926B1|2016-10-24|2018-01-30|International Business Machines Corporation|Static random access memorydensity scaling by using middle of lineflow|
    US11139295B2|2015-05-22|2021-10-05|Taiwan Semiconductor Manufacturing Co., Ltd.|Fin field effect transistordevice and method|JP2725773B2|1987-11-19|1998-03-11|三洋電機株式会社|Semiconductor integrated circuit and manufacturing method thereof|
    EP0516031A1|1991-05-29|1992-12-02|Ramtron International Corporation|Stacked ferroelectric memory cell and method|
    US5393712A|1993-06-28|1995-02-28|Lsi Logic Corporation|Process for forming low dielectric constant insulation layer on integrated circuit structure|
    US5470801A|1993-06-28|1995-11-28|Lsi Logic Corporation|Low dielectric constant insulation layer for integrated circuit structure and method of making same|
    US5486715A|1993-10-15|1996-01-23|Ixys Corporation|High frequency MOS device|
    JPH07235650A|1993-12-27|1995-09-05|Mitsubishi Electric Corp|Non-volatile semiconductor storage device|
    US5591673A|1995-07-05|1997-01-07|Taiwan Semiconductor Manufacturing Company Ltd.|Tungsten stud process for stacked via applications|
    US5943598A|1995-10-19|1999-08-24|Stmicroelectronics, Inc.|Integrated circuit with planarized dielectric layer between successive polysilicon layers|
    JP3281234B2|1995-11-08|2002-05-13|富士通株式会社|Semiconductor integrated circuit device and method of manufacturing the same|
    US5900668A|1995-11-30|1999-05-04|Advanced Micro Devices, Inc.|Low capacitance interconnection|
    US5892249A|1996-02-23|1999-04-06|National Semiconductor Corporation|Integrated circuit having reprogramming cell|
    US5840624A|1996-03-15|1998-11-24|Taiwan Semiconductor Manufacturing Company, Ltd|Reduction of via over etching for borderless contacts|
    JP3323055B2|1996-04-03|2002-09-09|株式会社東芝|Semiconductor device and manufacturing method thereof|
    US5639692A|1996-04-08|1997-06-17|Chartered Semiconductor Manufacturing Pte, Ltd.|Non-etch back SOG process using a metal via stud|
    US5767012A|1996-06-05|1998-06-16|Advanced Micro Devices, Inc.|Method of forming a recessed interconnect structure|
    US5801093A|1996-06-13|1998-09-01|Taiwan Semiconductor Manufacturing Company, Ltd.|Process for creating vias using pillar technology|
    US5798568A|1996-08-26|1998-08-25|Motorola, Inc.|Semiconductor component with multi-level interconnect system and method of manufacture|
    US5950102A|1997-02-03|1999-09-07|Industrial Technology Research Institute|Method for fabricating air-insulated multilevel metal interconnections for integrated circuits|
    US6107189A|1997-03-05|2000-08-22|Micron Technology, Inc.|Method of making a local interconnect using spacer-masked contact etch|
    US5837557A|1997-03-14|1998-11-17|Advanced Micro Devices, Inc.|Semiconductor fabrication method of forming a master layer to combine individually printed blocks of a circuit pattern|
    US5759906A|1997-04-11|1998-06-02|Industrial Technology Research Institute|Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits|
    US5970375A|1997-05-03|1999-10-19|Advanced Micro Devices, Inc.|Semiconductor fabrication employing a local interconnect|
    US5858869A|1997-06-03|1999-01-12|Industrial Technology Research Institute|Method for fabricating intermetal dielectric insulation using anisotropic plasma oxides and low dielectric constant polymers|
    US5869149A|1997-06-30|1999-02-09|Lam Research Corporation|Method for preparing nitrogen surface treated fluorine doped silicon dioxide films|
    JPH1145949A|1997-07-28|1999-02-16|Mitsubishi Electric Corp|Static semiconductor memory device and its manufacture|
    US5882983A|1997-12-19|1999-03-16|Advanced Micro Devices, Inc.|Trench isolation structure partially bound between a pair of low K dielectric structures|US6448631B2|1998-09-23|2002-09-10|Artisan Components, Inc.|Cell architecture with local interconnect and method for making same|
    EP0989609B1|1998-09-25|2005-02-09|STMicroelectronics S.r.l.|Multilevel Interconnect Structure|
    JP4570811B2|2001-04-27|2010-10-27|ルネサスエレクトロニクス株式会社|Semiconductor device|
    US6855624B1|2002-09-17|2005-02-15|Lsi Logic Corporation|Low-loss on-chip transmission line for integrated circuit structures and method of manufacture|
    US6969909B2|2002-12-20|2005-11-29|Vlt, Inc.|Flip chip FET device|
    US7038917B2|2002-12-27|2006-05-02|Vlt, Inc.|Low loss, high density array interconnection|
    DE10305365B4|2003-02-10|2005-02-10|Infineon Technologies Ag|Method and arrangement for contacting terminals of a bipolar transistor|
    JP4377640B2|2003-09-19|2009-12-02|株式会社半導体エネルギー研究所|Semiconductor device and manufacturing method thereof|
    US7176125B2|2004-07-23|2007-02-13|Taiwan Semiconductor Manufacturing Company, Ltd.|Method of forming a static random access memory with a buried local interconnect|
    JP2008078777A|2006-09-19|2008-04-03|Brother Ind Ltd|Printed matter management device|
    JP2008074068A|2006-09-25|2008-04-03|Brother Ind Ltd|Image forming apparatus|
    JP4197027B2|2006-09-28|2008-12-17|ブラザー工業株式会社|Image forming apparatus and program|
    JP2008084152A|2006-09-28|2008-04-10|Brother Ind Ltd|Image forming apparatus and program|
    JP2008085844A|2006-09-28|2008-04-10|Brother Ind Ltd|Data processing apparatus and recording medium|
    JP2008090340A|2006-09-29|2008-04-17|Brother Ind Ltd|Document data editing device, document preparation system, and program|
    JP4415984B2|2006-12-06|2010-02-17|ソニー株式会社|Manufacturing method of semiconductor device|
    US7608538B2|2007-01-05|2009-10-27|International Business Machines Corporation|Formation of vertical devices by electroplating|
    US8952547B2|2007-07-09|2015-02-10|Taiwan Semiconductor Manufacturing Company, Ltd.|Semiconductor device with contact structure with first/second contacts formed in first/second dielectric layers and method of forming same|
    US8035165B2|2008-08-26|2011-10-11|Taiwan Semiconductor Manufacturing Company, Ltd.|Integrating a first contact structure in a gate last process|
    US9263439B2|2010-05-24|2016-02-16|Infineon Technologies Americas Corp.|III-nitride switching device with an emulated diode|
    US8816403B2|2011-09-21|2014-08-26|Taiwan Semiconductor Manufacturing Co., Ltd.|Efficient semiconductor device cell layout utilizing underlying local connective features|
    US8947902B2|2012-03-06|2015-02-03|Taiwan Semiconductor Manufacturing Co., Ltd.|Semiconductor memory and method of making the same|
    US9349436B2|2012-03-06|2016-05-24|Taiwan Semiconductor Manufacturing Co., Ltd.|Semiconductor memory and method of making the same|
    KR102310122B1|2014-06-10|2021-10-08|삼성전자주식회사|Logic cell, integrated circuit including logic cell, and methods of manufacturing the same|
    US10031989B2|2014-11-18|2018-07-24|Globalfoundries Inc.|Integrated circuit performance modeling using a connectivity-based condensed resistance model for a conductive structure in an integrated circuit|
    US10128187B2|2016-07-11|2018-11-13|Globalfoundries Inc.|Integrated circuit structure having gate contact and method of forming same|
    法律状态:
    2002-11-07| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2006-01-12| FPAY| Fee payment|Year of fee payment: 4 |
    2010-05-20| FPAY| Fee payment|Year of fee payment: 8 |
    2014-04-30| FPAY| Fee payment|Year of fee payment: 12 |
    2014-05-08| AS| Assignment|Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031 Effective date: 20140506 |
    2015-04-03| AS| Assignment|Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LSI CORPORATION;REEL/FRAME:035390/0388 Effective date: 20140814 |
    2016-02-02| AS| Assignment|Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 Owner name: LSI CORPORATION, CALIFORNIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 |
    2016-02-11| AS| Assignment|Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 |
    2017-02-03| AS| Assignment|Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 |
    2017-12-17| AS| Assignment|Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;BROADCOM CORPORATION;REEL/FRAME:044886/0001 Effective date: 20171208 Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;BROADCOM CORPORATION;REEL/FRAME:044886/0608 Effective date: 20171208 |
    2018-02-01| AS| Assignment|Owner name: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERA Free format text: SECURITY INTEREST;ASSIGNORS:HILCO PATENT ACQUISITION 56, LLC;BELL SEMICONDUCTOR, LLC;BELL NORTHERN RESEARCH, LLC;REEL/FRAME:045216/0020 Effective date: 20180124 |
    优先权:
    申请号 | 申请日 | 专利标题
    US09/081,403|US6239491B1|1998-05-18|1998-05-18|Integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level, and process for making same|
    US09/790,821|US6486056B2|1998-05-18|2001-02-22|Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level|US09/790,821| US6486056B2|1998-05-18|2001-02-22|Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level|
    [返回顶部]